Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the ...

Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down.

Power consumption is a crucial consideration for all types of electronics. As critical power components used in a wide range of electronic products, power MOSFET and other types of power semiconductor ...

BEDFORD, Mass. & SEOUL, South Korea--(BUSINESS WIRE)--Silicon wafer manufacturer 1366 Technologies together with its strategic partners, Hanwha Q CELLS Malaysia Sdn. Bhd. and parent company Hanwha Q ...

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In an update to its International Technology Roadmap for Photovoltaics, German engineering association the VDMA notes standardization of wafer size is a topic of great interest to the country’s PV ...

Concept of mask/wafer co-optimization by moving the shot with mask and wafer double simulation to minimize wafer error. VSB shot configurations and its corresponding ...

FREMONT, Calif., March 18, 2020 (GLOBE NEWSWIRE) -- ACM Research, Inc. (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging ...

NexWafe’s EpiNex solar wafers achieved 24.4% efficiency on a commercial M6 heterojunction (HJT) cell line, for the first time delivering performance parity with conventional CZ wafers. Modules made ...

Rapidus on Friday announced that it had begun prototyping of test wafers with 2nm gate-all-around (GAA) transistor structures at its IIM-1 facility in Japan. The company confirmed that early test ...

German wafer manufacturer NexWafe GmbH announced it achieved a power conversion efficiency of 24.4% for a heterojunction (HJT) solar cell built with its ultrathin wafers. The company said the ...